The invention relates generally to interconnect structures within microelectronic structures. More particularly, the invention relates to methods for efficiently fabricating interconnect structures within microelectronic structures.
Microelectronic structures, such as but not limited to semiconductor structures, are typically fabricated using microelectronic substrates within, upon and/or over which are located and formed microelectronic devices. The microelectronic devices are connected and interconnected using patterned conductor layers that are separated by dielectric layers. Such sub-structures that comprise such patterned conductor layers that are separated by dielectric layers within microelectronic structures are conventionally understood within the microelectronic fabrication art as interconnect structures.
As microelectronic fabrication technology has advanced, the complexity of interconnect structures has also increased. Thus, interconnect structures within microelectronic structures typically comprise several interconnecting patterned conductor layers that are separated by dielectric layers that are interposed between the several interconnecting patterned conductor layers. In order to provide for optimal performance of interconnect structures, patterned conductor layers within interconnect structures typically comprise copper containing conductor materials that provide for enhanced microelectronic circuit speed, while dielectric layers within interconnect structures typically comprise comparatively low dielectric constant dielectric materials (i.e., having a dielectric constant from 1.0 to 4.3) that provide for reduced cross-talk between adjacent patterned conductor layers within an interconnect structure.
While copper containing conductor materials and comparatively low dielectric constant dielectric materials are thus desirable within the microelectronic fabrication art for fabricating interconnect structures with enhanced performance, copper containing conductor materials and low dielectric constant dielectric materials are nonetheless not entirely without problems in the microelectronic fabrication art for fabricating interconnect structures with enhanced performance. In that regard, a density of patterned conductor layers within an interconnect structure may provide for reflective based processing difficulties within an interconnect structure when fabricating an overlying patterned conductor layer within the interconnect structure. In addition, low dielectric constant dielectric materials are also often difficult to effectively and reproducibly pattern absent damage while using conventional dry plasma etch methods.
Thus, desirable are interconnect structures within microelectronic structures and methods for fabricating interconnect structures within microelectronic structures that provide for readily fabricated interconnect structures with enhanced interconnect structure performance.